Integrated circuits, also referred to as "chips", typically include logic chips, memory chips, combined logic and memory chips such as microprocessor chips, and other chips. Wafer size integrated circuits have also been proposed. In the present state of the art integrated circuits have become very complex. For example, an Ultra Large Scale Integration (ULSI) chip may include several million devices thereon.
As the manufacture of integrated circuits has become more complex, testing of integrated circuits has also become more difficult due to the large number of interconnected devices thereon. In fact, in the present state of the art, testing consumes significant portions of the development cost of any new integrated circuit.
Testing of high density integrated circuits has become increasingly difficult because testing cannot typically rely on the external input and output (I/O) pins or pads of the integrated circuit. In other words, to fully test the integrated circuit within a reasonable amount of time, access to internal sites of the integrated circuit are necessary. Internal sites must be accessed in order to apply internal test signals and to measure responses to the internal test signals.
The art has developed a number of techniques for accessing the internal sites of an integrated circuit. Unfortunately, each of these techniques impacts the manufacture or operation of the integrated circuit. For example, some integrated circuits have included a large number of test I/O pins which permit access to internal sites of the integrated circuit. Unfortunately, the need for test I/O pins limits the number of active pins that can be provided for normal operations. As the size of the integrated circuit devices shrinks and the number of devices per number of pins increases, it is more difficult to provide many separate test pins.
Other approaches have used an internal "scan path" to thread registers throughout an integrated circuit to form a large serial shift register. The shift register can be used for transferring test data to internal sites of the circuit. Unfortunately, the shift registers and their control circuits consume some of the active chip area ("real estate") and thereby limit the real estate available for normal integrated circuit functions. The shift registers and their control circuits can also degrade chip performance, by adding capacitive loading to the integrated circuit during normal operations. The scan path method also serializes the test process, and typically results in large test vector sets which increases the test application time. Chip partitioning approaches have also been used to partition the active circuitry in the chip into a number of subcircuits for accessing the internal sites. Again, however, partitioning requires additional test pins and/or internal test circuitry thereby limiting performance.
The art has attempted to provide access to internal sites without an undue real estate or I/O pin penalty by using optical testing techniques. For example, U.S. Pat. No. 4,053,833 to Malmberg et al. describes a contactless integrated circuit testing technique in which a number of photodiode switches are fabricated in the integrated circuit. The photodiodes allow the integrated circuit to be tested in terms of partitioned modules. One or more light beams are used to selectively adapt the photodiodes to conduct. Unfortunately, this approach is not practical for high density integrated circuits because too much real estate is occupied and capacitive loading is produced by the photodiodes themselves, and because it is often not feasible to fabricate photodiodes on the same chip as high density logic and memory devices.
In an article entitled Holographic Optical Interconncts for VLSI, published in Optical Engineering, Vol. 25, No. 10, Oct. 1986, pp. 1109-1117, Bergman et al. suggest that microcircuit testing techniques based on optical access to specific locations on a chip can be developed. In fact, holograms have been used to program a logic array, as shown in U.S. Pat. No. 4,760,249 to Baskett entitled Logic Array Having Multiple Optical Logic Inputs, and holograms have been used for optical clock distribution in an integrated circuit as described in an article entitled Optical Clock Distribution to Silicon Chips, published in Optical Engineering, Vol. 25, No. 10, Oct. 1986, pp. 1103-1108 by Clymer et al.
In conclusion, while the art has suggested that optical techniques may be used to enhance the testability of high density integrated circuits, to the best of Applicants' knowledge the art has not heretofore suggested an electro-optical method and apparatus for testing integrated circuits which requires little overhead in terms of test pins, chip real estate, or performance degradation.